(a) Field of the Invention
This invention relates to an integrated semiconductor memory device called one transistor/cell type, including memory, each consisting of one storage capacitor and one insulated gate field effect transistor (IG FET).
(b) Description of the Prior Art
It is well known to implement a random access memory (RAM) by employing an integrated semiconductor memory device in which the IG FET is used as the principal element. Particularly, one of the most popular RAM's employs a dynamic one transistor/cell type memory device which has a memory cell consisting of one storage capacitor and one IG FET.
This one transistor/cell type memory device provides a memory function in accordance with the charges in the storage capacitor, and the IG FET in the cell functions as the transfer gate for controlling the input and output of the charges to/from the storage capacitor. In this memory cell, charge stored in the storage capacitor gradually decreases by leak charge, and generally charge is supplied to the storage capacitor via the transfer gate every so often, during a so-called "refresh" period.
The actual integrated semiconductor memory device of this type is composed of a memory cell array comprising a semiconductor substrate on which are found a number of the above-mentioned memory cells and peripheral circuits, having a decoder, a sense amplifier, a clock generator and other elements associated therewith. The peripheral circuit is principally composed of the IG FET which is substantially the same as the IG FET of the transfer gate in the memory cell.
In general, these IG FETs are designed to have a gate threshold voltage level of 1 to 1.5 V in the abovementioned memory device, considering operation speed, power consumption, noise margin, etc. This gate threshold value is a value suitable for receiving, at the input of the peripheral circuit, signal levels outside the TTL level in the range from 0.4 to 2.4 volt.
When a word line connected to the transfer gate of the memory cell is of 0 level (namely, the memory cell is in the "unselected" condition) the transfer gate is in the "nonconductive" condition, and the storage capacitor is separated from the bit line by means of the transfer gate. In the actual memory device, a low level pulsating noise is often induced on the bit line or word line during the "unselected" period. This pulsating noise can contribute to the discharge of the storage capacitor to the bit line through the transfer gate, even when its amplitude is very low. In practice, this is because the IG FET allows even a minute current to flow, even when a voltage which is considerably lower than the gate threshold is applied to the gate. This problem is not effectively remedied by giving a large capacitance value to the storage capacitor so that a little charge loss can be ignored. This is because a storage capacitor having a large capacitance value requires a wider area of the substrate, and this brings deterioration of the integration density of the memory device.
A pulsating noise on the bit line or word line is, for example, induced when the other bit line or word line transition between the "unselected" and "selected" condition. In the practical memory device, in which the gate threshold of the transfer gate is in the range from 1 to 1.5 volt, it has often been observed that data is destroyed as a result of the above-mentioned phenomenon.